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THC63LVD823B_rev.3.1_e copyright?2011 thin e electronics, inc. 1/21 thine electronics, inc. THC63LVD823B 160mhz 51bits lvds transmitter general description the THC63LVD823B tran smitter is designed to sup- port single link transmission between host and flat panel display and dual link transmission between host and flat panel display up to 1080p/qxga resolu- tions. the THC63LVD823B converts 51bits of cmos/ttl data into lvds (low voltage differential signaling) data stream. the transmitter can be programmed for ris- ing edge or falling edge clocks through a dedicated pin. in dual link, the transmit clock frequency of 160mhz, 51bits of rgb data are transmitted at an effective rate of 1.12gbps per lvds channel. features ? wide dot clock range suited for tv signal (480p- 1080p), pc signal (vga-qxga) ttl/cmos input: 10-160mhz lvds output: 20-160mhz ? pll requires no external components ? flexible input/output mode 1. single/dual ttl in , single/dual lvds out 2. double edge input for single ttl in/dual lvds out ? clock edge selectable ? 2 lvds data mapping for simplifying pcb layout. ? pseudo random pattern generation circuit ? supports reduced swing lvds for low emi ? power down mode ? low power single 3.3v cmos design ? 1.2 up to 3.3v tolerant data inputs to connect directly to low power,low voltage application and graphic processor. ? backward compatible with thc63lvd823/ thc63lvd823a ? 100pin tqfp block diagram parallel to serial pll ta1 +/- tb1 +/- tc1 +/- td1 +/- tclk1 +/- /pdwn (20 to 160mhz) transmitter clock in (10 to 160mhz) r1[7:0] lvds output 24 data port1 tclk2 +/- (n/c) port1 g1[7:0] b1[7:0] hsync 28 data formatter 28 r/f 1) demux 2) mux vsync de map r2[7:0] 24 data port2 g2[7:0] b2[7:0] 3 rs mode[1:0] prbs parallel to serial ta2 +/- tb2 +/- tc2 +/- td2 +/- lvds output port2 o/e ddrn
copyright?2011 thine electronics, inc. 2/21 thine electronics, inc. THC63LVD823B_rev.3.1_e pin out (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 b24 b25 vcc gnd b26 b27 hsync vsync de clkin r/f rs ddrn map mode1 mode0 o/e gnd /pdwn prbs reserved n/c pgnd pvcc pgnd lgnd td2+ td2- tclk2- tc2+ tc2- tb2+ tb2- ta2+ ta2- lgnd lgnd b14 gnd vcc b13 b12 b11 b10 g17 g16 g15 g14 g13 g12 g11 g10 r17 r16 r15 r14 gnd vcc r13 r12 r10 b15 b16 b17 r20 r21 r22 r23 r24 r25 r26 r27 vcc gnd g20 g21 g22 g23 g24 g25 g26 g27 b20 b21 b22 b23 tclk2+ td1+ td1- tc1+ tc1- tclk1+ tclk1- tb1+ tb1- ta1- ta1+ lvcc lvcc r11
copyright?2011 thine electronics, inc. 3/21 thine electronics, inc. THC63LVD823B_rev.3.1_e pin description pin name pin # type description ta1+, ta1- 48, 49 lvds out the 1st link. the 1st pixel output data when dual-link. tb1+, tb1- 46, 47 tc1+, tc1- 43, 44 td1+, td1- 39, 40 tclk1+, tclk1- 41, 42 lvds out lvds clock out for 1st and 2nd link. ta2+, ta2- 36, 37 lvds out the 2nd link. these pins are disabled when single link. tb2+, tb2- 34, 35 tc2+, tc2- 31, 32 td2+, td2- 27, 28 tclk2+, tclk2- 29, 30 lvds out additional lvds clock out. identical to tclk1+,-. no connect if not used. r17 ~ r10 60 -57, 54 - 51 in the 1st pixel data inputs. g17 ~ g10 68 - 61 b17 ~ b10 78 - 73, 70, 69 r27 ~ r20 86 - 79 in the 2nd pixel data inputs. g27 ~ g20 96 - 89 b27 ~ b20 6, 5, 2, 1, 100 - 97 de 9 in data enable input. vsync 8 in vsync input. hsync 7 in hsync input. clkin 10 in clock input. r/f 11 in input clock trigger ing edge select. h: rising edge, l: falling edge rs 12 in lvds swing mode, v ref select. see fig4 - 5. map 14 in lvds mapping table select. see fig7 to 8 and table4 to 7. mode1, mode0 15, 16 in rs lvds swing small swing input support v ihm 350mv n/a v imm 350mv rs=v ref a a. v ref is input reference voltage. v ilm 200mv n/a map mapping mode v ihm mapping mode1 v ilm mapping mode2 v imm reserved pixel data mode. mode 1 mode0 mode l l dual link (dual-in/dual-out) h l dual link (single-in/dual-out) l h single link (dual-in/single-out) h h single link (single-in/single-out)
copyright?2011 thine electronics, inc. 4/21 thine electronics, inc. THC63LVD823B_rev.3.1_e a: setting the prbs pin high enables the internal test pattern generator. it generates pseudo-random bit sequence of 2 23 -1. the generated prbs is fed into input data latches, fo rmatted as vga video like data, encoded and serialized into txout output. this func tion is normally to be used for analyzing the signal integrity of the transmission channel including pcb traces, connectors, and cables. o/e 17 in output enable. h: output enable, l: output disable (all outputs are hi-z). /pdwn 19 in h: normal operation, l: power down (all outputs are hi-z) prbs a 20 in prbs (pseudo-random binary sequence) generator is active in order to evaluate eye patterns when mode<1:0> = ll (dual-in/dual-out mode). h: prbs generator is enable. l: normal operation reserved 21 in must be tied to gnd. ddrn 13 in ddr function is active when mode<1:0> = hl (single-in/dual-out mode). open or h: ddr (double edge input) function disable. l: ddr (double edge input) function enable. n/c 22 must be open. vcc 3, 55, 71, 87 power power supply pins for ttl inputs and digital circuitry. gnd 4, 18, 56, 72, 88 ground ground pins for ttl inputs and digital circuitry. lvcc 33, 45 power power supply pins for lvds outputs. lgnd 26, 38, 50 ground ground pins for lvds outputs. pvcc 24 power power supply pin for pll circuitry. pgnd 23, 25 ground ground pins for pll circuitry. pin name pin # type description pin description (continued)
copyright?2011 thine electronics, inc. 5/21 thine electronics, inc. THC63LVD823B_rev.3.1_e absolute maximum ratings recommended operating conditions supply voltage (v cc ) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) lvds transmitter output voltage -0.3v ~ (v cc + 0.3v) output current -30ma ~ 30ma junction temperature +125 storage temperature range -55 ~ +125 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 2.4w parameter min. typ max units all supply voltage 3.0 3.3 3.6 v operating ambient temperature -20 70 clock frequency mode<1:0>=ll dual-in/dual-out input 20 160 mhz lvds output 20 160 mhz mode<1:0>=lh dual-in/single-out input 10 80 mhz lvds output 20 160 mhz mode<1:0>=hl single-in/dual-out single edge input (ddrn =open/h) input 40 160 mhz lvds output 20 80 mhz double edge input (ddrn=l) input 20 80 mhz lvds output 20 80 mhz mode<1:0>=hh single-in/single-out input 20 160 mhz lvds output 20 160 mhz c c c c c c
THC63LVD823B_rev.3.1_e copyright?2011 thin e electronics, inc. 6/21 thine electronics, inc. electrical characteristics cmos/ttl dc specifications v cc = vcc=pvcc=lvcc lvds transmitter dc specifications v cc = vcc=pvcc=lvcc symbol parameter conditions min. typ. max. units v ih a a. clkin,r10~r17,g10~g1 7,b10~b17,r20~r 27,g20~g27,b20~b2 7,de,hsync,vsync high level data input voltage rs=v ihm or v ilm 2.0 v cc v rs=v imm v ref b +0.1 b. v ref is input voltage of rs pin. v v il a low level data input voltage rs=v ihm or v ilm gnd 0.8 v rs=v imm v ref -0.1 v v ihc c c. r/f,ddrn,mode0,mode1,o/e,pdwn,prb s high level control input voltage 2.0 v cc v v ilc c low level control input voltage gnd 0.8 v v ihm d high level contro l input voltage 0.8v cc v cc v v imm d d. rs,map middle level control input voltage 0.6 1.4 v v ilm d low level control input voltage gnd 0.08v cc v i inc input current (except ddrn) a i incd input current (only ddrn) a symbol parameter conditions min. typ. max. units vod differential output voltage rl=100 normal swing rs= v cc 250 350 450 mv reduced swing rs= gnd 100 200 300 mv vod change in vod between complementary output states rl=100 35 mv voc common mode voltage 1.125 1.25 1.375 v voc change in voc between complementary output states 35 mv i os output short circuit cu rrent vout=gnd, rl=100 -24 ma i oz output tri-state current /pdwn=gnd, vout=gnd to v cc a gnd v in v cc ? 10 gnd v in v cc ? 20 10
copyright?2011 thine electronics, inc. 7/21 thine electronics, inc. THC63LVD823B_rev.3.1_e electrical characteristics (continued) supply current v cc = vcc=pvcc=lvcc symbol parameter condition typ. max. units i tccw transmitter supply current (worst case pattern) fig1. rl=100 cl=5pf rs=v cc mode<1:0>=hh single-in/single-out clkin=65mhz 86 ma clkin=85mhz 100 ma clkin=135mhz 122 ma clkin=160mhz t.b.d ma mode<1:0>=hl single-in/dual-out ddrn=h or open ddr input off clkin=65mhz 114 ma clkin=85mhz 116 ma clkin=135mhz 155 ma clkin=150mhz 168 ma clkin=160mhz t.b.d ma mode<1:0>=hl single-in/dual-out ddrn=l ddr input on clkin=32.5mhz 114 ma clkin=42.5mhz 118 ma clkin=67.5mhz 155 ma clkin=75mhz 167 ma clkin=80mhz t.b.d ma mode<1:0>=lh dual-in/single-out clkin=32.5mhz 84 ma clkin=42.5mhz 98 ma clkin=67.5mhz 120 ma clkin=80mhz t.b.d ma mode<1:0>=ll dual-in/dual-out clkin=65mhz 144 ma clkin=85mhz 171 ma clkin=135mhz 217 ma clkin=160mhz t.b.d ma i tccs transmitter power down supply current /pdwn = l, all inputs = fixed l or h 50 a fig1. test pattern txy+ x= a, b, c, d y=1,2 tclk1+ (lvds output full toggle pattern)
THC63LVD823B_rev.3.1_e copyright?2011 thin e electronics, inc. 8/21 thine electronics, inc. switching characteristics v cc = vcc=pvcc=lvcc symbol parameter min. typ. max. units t tcip clk in period(fig4,5) 6.25 100 ns t tch clk in high time(fig4,5) 0.35t tcip 0.5t tcip 0.65t tcip ns t tcl clk in low time(fig4,5) 0.35t tcip 0.5t tcip 0.65t tcip ns t ts ttl data setup to clk in(fig4,5) 2.5 ns t th ttl data hold from ckl in(fig4,5) 0.0 ns t tcd clk in to tclk+/ - delay(fig4,5) mode<1:0>=ll dual-in/dual-out (4+3/7)t tcip +2.6 (4+3/7)t tcip +7.5 ns t tcop clk out period(fig6) 6.25 50 ns t lvt lvds transition time(fig2) 0.6 1.5 ns t top1 output data position0 (fig6) t tcop = 6.25ns~20ns -0.15 0.0 +0.15 ns t top0 output data position1 (fig6) ns t top6 output data position2 (fig6) ns t top5 output data position3 (fig6) ns t top4 output data position4 (fig6) ns t top3 output data position5 (fig6) ns t top2 output data position6 (fig6) ns t tpll phase lock time(fig3) 10.0 ms t deint de input period (fig3-1) single-in / dual-out, ddr off mode only(mode<1:0>=hl, ddrn =open or h) 4t tcip ttcip*(2n) a a. refer to fig3-1 for details. ns t deh de high time (fig3-1) single-in / dual-out, ddr off mode only(mode<1:0>=hl, ddrn =open or h) 2t tcip ttcip*(2m) a ns t del de low time(fig3-1) single-in / dual-out, ddr off mode only(mode<1:0>=hl, ddrn =open or h) 2t tcip ns t tcop 7 --------------- 0 . 1 5 ? t tcop 7 --------------- t tcop 7 --------------- 0 . 1 5 + 2 t tcop 7 --------------- 0 . 1 5 ? 2 t tcop 7 --------------- 2 t tcop 7 --------------- 0 . 1 5 + 3 t tcop 7 --------------- 0 . 1 5 ? 3 t tcop 7 --------------- 3 t tcop 7 --------------- 0 . 1 5 + 4 t tcop 7 --------------- 0 . 1 5 ? 4 t tcop 7 --------------- 4 t tcop 7 --------------- 0 . 1 5 + 5 t tcop 7 --------------- 0 . 1 5 ? 5 t tcop 7 --------------- 5 t tcop 7 --------------- 0 . 1 5 + 6 t tcop 7 --------------- 0 . 1 5 ? 6 t tcop 7 --------------- 6 t tcop 7 --------------- 0 . 1 5 +
copyright?2011 thine electronics, inc. 9/21 thine electronics, inc. THC63LVD823B_rev.3.1_e ac timing diagrams 2.0v t tpll clkin /pdwn tclkx+/- v diff =0v fig3. pll lock time x=1,2 5pf 20% 80% 20% 80% t lvt t lvt v diff 100 v diff =(ta+)-(ta-) ta+ ta- lvds output load fig2. lvds output load and transition time clkin de t deint t deh t del note: in single-in/dual-out, ddr off mo de (mode<1:0>=hl, ddrn =open or h), the period between rising edges of de (t deint ), high time of de (t deh ) t tcip fig3-1. single in / dual out, ddr off mode de input timing should always satisf y following equations. t deint = ttcip * (2n) m, n =integer t deh = ttcip * (2m)
copyright?2011 thine electronics, inc. 10/21 thine electronics, inc. THC63LVD823B_rev.3.1_e ac timing diagrams (continued) fig4. clkin period, high/low time, setup/hold timing t tcip t ts t th t tch t tcl clkin t tcd voc v ref v ref v ref v ref v ref note: clkin: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. gnd gnd rxn, gxn, bxn hsync vsync de x=1,2 n=0-7 current data tclkx+/- x=1,2 current data txy+/- x=1,2 y= a, b, c, d vod vcc vcc rs pin vod vref v ihm 350mv vcc/2 v imm input voltage of rs pin v ilm 200mv vcc/2 fig5. clkin period, high/low time , setup/hold timing for double edge input mode (ddr) note: clkin: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. mode<1:0>=hl,ddrn=l current data txy+/- x=1,2 y= a, b, c, d v ref v ref 1st pixel data 2nd pixel data gnd vod vcc vcc t ts t th t ts t th t tcip t tch t tcl clkin t tcd voc v ref v ref v ref gnd rxn, gxn, bxn vsync de x=1,2 n=0-7 tclkx+/- x=1,2 rs pin vod vref v ihm 350mv vcc/2 v imm input voltage of rs pin v ilm 200mv vcc/2 hsync
copyright?2011 thine electronics, inc. 11/21 thine electronics, inc. THC63LVD823B_rev.3.1_e ac timing diagrams (continued) v diff = 0v tyx+/- tyx6 tyx5 tyx4 tyx3 tyx2 tyx1 tyx0 tyx6 tyx5 tyx4 tyx3 tyx2 tyx1 v diff = 0v t top2 t top3 t top4 t top5 t top6 t top0 t top1 t tcop tclkx+ x = 1,2 y = a,b,c,d note: v diff = (tyx+) - (tyx-), (tclkx+) - (tclkx-) fig6. lvds output data position
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 12/21 thine electronics, inc. input data mapping ? table1. input color data naming rule ? table2. ttl/cmos input data mapping (single-in mode, mode1=h) x y z description x=r red color data x=g green color data x=b blue color data y= none single pixel y=e dual pixel 1st pixel data y=o 2nd pixel data z=0-7 bit number 0: lsb (least significant bit) 7: msb (most significant bit) data signals transmitter input pin names r0 r10 r1 r11 r2 r12 r3 r13 r4 r14 r5 r15 r6 r16 r7 r17 g0 g10 g1 g11 g2 g12 g3 g13 g4 g14 g5 g15 g6 g16 g7 g17 b0 b10 b1 b11 b2 b12 b3 b13 b4 b14 b5 b15 b6 b16 b7 b17
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 13/21 thine electronics, inc. input data mapping (continued) ? table3. ttl/cmos input data mapping (dual-in mode, mode1=l) data signals transmitter input pin names data signals transmitter input pin names re0 r10 ro0 r20 re1 r11 ro1 r21 re2 r12 ro2 r22 re3 r13 ro3 r23 re4 r14 ro4 r24 re5 r15 ro5 r25 re6 r16 ro6 r26 re7 r17 ro7 r27 ge0 g10 go0 g20 ge1 g11 go1 g21 ge2 g12 go2 g22 ge3 g13 go3 g23 ge4 g14 go4 g24 ge5 g15 go5 g25 ge6 g16 go6 g26 ge7 g17 go7 g27 be0 b10 bo0 b20 be1 b11 bo1 b21 be2 b12 bo2 b22 be3 b13 bo3 b23 be4 b14 bo4 b24 be5 b15 bo5 b25 be6 b16 bo6 b26 be7 b17 bo7 b27
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 14/21 thine electronics, inc. lvds output data mapping tx1+/- tclk1+ previous cycle current cycle fig7. ttl data inputs mapped to lvds outputs mode0= h (single-out mode) x= a, b, c, d tx11(n-1) tx10(n-1) tx16(n) tx15(n) tx14(n) tx13(n) tx12(n) tx11(n) tx10(n) tx16(n+1) (2nd pixel data) (1st pixel data) next cycle (2nd pixel data) tx1+/- tclk1+ previous cycle current cycle fig8. ttl data inputs mapped to lvds outputs mode0= l (dual-out mode) x= a, b, c, d tx11(n-1) tx10(n-1) tx16(n) tx15(n) tx14(n) tx13(n) tx12(n) tx11(n) tx10(n) tx16(n+1) tx21(n-1) tx20(n-1) tx26(n) tx25(n) tx24(n) tx23(n) tx22(n) tx21(n) tx20(n) tx26(n+1) tx2+/- x= a, b, c, d
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 15/21 thine electronics, inc. lvds output data mapping (continued) ? table4. lvds output data mapping (single-in/single-out, mode<1:0>=hh) lvds output data mapping mode (input pin name) mode1 map=h mode2 map=l ta10 r12 r10 ta11 r13 r11 ta12 r14 r12 ta13 r15 r13 ta14 r16 r14 ta15 r17 r15 ta16 g12 g10 tb10 g13 g11 tb11 g14 g12 tb12 g15 g13 tb13 g16 g14 tb14 g17 g15 tb15 b12 b10 tb16 b13 b11 tc10 b14 b12 tc11 b15 b13 tc12 b16 b14 tc13 b17 b15 tc14 hsync hsync tc15 vsync vsync tc16 de de td10 r10 r16 td11 r11 r17 td12 g10 g16 td13 g11 g17 td14 b10 b16 td15 b11 b17 td16 n/a n/a
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 16/21 thine electronics, inc. lvds output data mapping (continued) ? table5. lvds output data mapping (single-in/d ual-out, ddr on/off, mode<1:0>=hl, ddrn =open/h/l) lvds output data (1st link) mapping mode (input pin name) lvds output data (2nd link) mapping mode (input pin name) mode1 map=h mode2 map=l mode1 map=h mode2 map=l ta10 r12 r10 ta20 r12 r10 ta11 r13 r11 ta21 r13 r11 ta12 r14 r12 ta22 r14 r12 ta13 r15 r13 ta23 r15 r13 ta14 r16 r14 ta24 r16 r14 ta15 r17 r15 ta25 r17 r15 ta16 g12 g10 ta26 g12 g10 tb10 g13 g11 tb20 g13 g11 tb11 g14 g12 tb21 g14 g12 tb12 g15 g13 tb22 g15 g13 tb13 g16 g14 tb23 g16 g14 tb14 g17 g15 tb24 g17 g15 tb15 b12 b10 tb25 b12 b10 tb16 b13 b11 tb26 b13 b11 tc10 b14 b12 tc20 b14 b12 tc11 b15 b13 tc21 b15 b13 tc12 b16 b14 tc22 b16 b14 tc13 b17 b15 tc23 b17 b15 tc14 hsync hsync tc24 hsync hsync tc15 vsync vsync tc25 vsync vsync tc16 de de tc26 de de td10 r10 r16 td20 r10 r16 td11 r11 r17 td21 r11 r17 td12 g10 g16 td22 g10 g16 td13 g11 g17 td23 g11 g17 td14 b10 b16 td24 b10 b16 td15 b11 b17 td25 b11 b17 td16 n/a n/a td26 n/a n/a de r1n,g1n,b1n fig9. the decision rule of 1st pixel data in single in/dual out ddr off 1st pixel data 2nd pixel data 1st pixel data 2nd pixel data n=0 - 7 hsync vsync gnd vcc vcc gnd (mode<1:0>=hl, ddrn =open or h)
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 17/21 thine electronics, inc. lvds output data mapping (continued) ? table6. lvds output data mapping (dual-in/single-out, mode<1:0>=lh) lvds output data (1st pixel) mapping mode (input pin name) lvds output data (2nd pixel) mapping mode (input pin name) mode1 map=h mode2 map=l mode1 map=h mode2 map=l ta10(n) r12 r10 ta10(n+1) r22 r20 ta11(n) r13 r11 ta11(n+1) r23 r21 ta12(n) r14 r12 ta12(n+1) r24 r22 ta13(n) r15 r13 ta13(n+1) r25 r23 ta14(n) r16 r14 ta14(n+1) r26 r24 ta15(n) r17 r15 ta15(n+1) r27 r25 ta16(n) g12 g10 ta16(n+1) g22 g20 tb10(n) g13 g11 tb10(n+1) g23 g21 tb11(n) g14 g12 tb11(n+1) g24 g22 tb12(n) g15 g13 tb12(n+1) g25 g23 tb13(n) g16 g14 tb13(n+1) g26 g24 tb14(n) g17 g15 tb14(n+1) g27 g25 tb15(n) b12 b10 tb15(n+1) b22 b20 tb16(n) b13 b11 tb16(n+1) b23 b21 tc10(n) b14 b12 tc10(n+1) b24 b22 tc11(n) b15 b13 tc11(n+1) b25 b23 tc12(n) b16 b14 tc12(n+1) b26 b24 tc13(n) b17 b15 tc13(n+1) b27 b25 tc14(n) hsync hsync tc14(n+1) hsync hsync tc15(n) vsync vsync tc15(n+1) vsync vsync tc16(n) de de tc16(n+1) de de td10(n) r10 r16 td10(n+1) r20 r26 td11(n) r11 r17 td11(n+1) r21 r27 td12(n) g10 g16 td12(n+1) g20 g26 td13(n) g11 g17 td13(n+1) g21 g27 td14(n) b10 b16 td14(n+1) b20 b26 td15(n) b11 b17 td15(n+1) b21 b27 td16(n) n/a n/a td16(n+1) n/a n/a
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 18/21 thine electronics, inc. lvds output data mapping (continued) ? table7. lvds output data mapping (dual-in/dual-out, mode<1:0>=ll) lvds output data (1st link) mapping mode (input pin name) lvds output data (2nd link) mapping mode (input pin name) mode1 map=h mode2 map=l mode1 map=h mode2 map=l ta10 r12 r10 ta20 r22 r20 ta11 r13 r11 ta21 r23 r21 ta12 r14 r12 ta22 r24 r22 ta13 r15 r13 ta23 r25 r23 ta14 r16 r14 ta24 r26 r24 ta15 r17 r15 ta25 r27 r25 ta16 g12 g10 ta26 g22 g20 tb10 g13 g11 tb20 g23 g21 tb11 g14 g12 tb21 g24 g22 tb12 g15 g13 tb22 g25 g23 tb13 g16 g14 tb23 g26 g24 tb14 g17 g15 tb24 g27 g25 tb15 b12 b10 tb25 b22 b20 tb16 b13 b11 tb26 b23 b21 tc10 b14 b12 tc20 b24 b22 tc11 b15 b13 tc21 b25 b23 tc12 b16 b14 tc22 b26 b24 tc13 b17 b15 tc23 b27 b25 tc14 hsync hsync tc24 hsync hsync tc15 vsync vsync tc25 vsync vsync tc16 de de tc26 de de td10 r10 r16 td20 r20 r26 td11 r11 r17 td21 r21 r27 td12 g10 g16 td22 g20 g26 td13 g11 g17 td23 g21 g27 td14 b10 b16 td24 b20 b26 td15 b11 b17 td25 b21 b27 td16 n/a n/a td26 n/a n/a
THC63LVD823B_rev.3.1_e copyright?2011 thine electronics, inc. 19/21 thine electronics, inc. note 1)cable connection and disconnection don't connect and disconnec t the lvds cable, when the powe r is supplied to the system. 2)gnd connection connect the each gnd of the pcb which THC63LVD823B and lvds-rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3)multi drop connection multi drop connection is not recommended. 4)asynchronous use asynchronous use such as following systems are not recommended. lvds-rx THC63LVD823B lvds-rx tclk+ tclk- THC63LVD823B THC63LVD823B ic clkout clkout data data lvds-rx lvds-rx ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVD823B THC63LVD823B ic tclk+ tclk- tclk+ tclk- clkout clkout data data ic
copyright?2011 thine electronics, inc. 20/21 thine electronics, inc. THC63LVD823B_rev.3.1_e package seating plane 0.25mm gage plane 16.00 bsc 14.00 bsc 16.00 bsc 14.00 bsc 0 7.0 s 0.10 s 0.20 bsc 0.60 +/-0.15 0.08r min 0.08r 0.20r 1.20 max 1.00 +/-0.05 0.05 0.15 1.00 ref 0.09 0.20 unit mm 0.50 bsc 0.20 +0.07/-0.03
copyright?2011 thine electronics, inc. 21/21 thine electronics, inc. THC63LVD823B_rev.3.1_e notices and requests 1.)the product specifications described in this mate rial are subject to cha nge without prior notice. 2.)the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions s hould be found in this mate rial, we may not be able to correct them immediately. 3.)this material contains our c opy right, know-how or other pr oprietary. copying or disclosing to third parties the contents of this material without our prior perm ission is prohibited. 4.)note that if infringe ment of any third party' s industrial ownership s hould occur by using this product, we will be exempted from the responsibil ity unless it directly re lates to the production pro- cess or functions of the product. 5.)this product is presumed to be used for general electric eq uipment, not for the applications which require very high reliability (including medi cal equipment directly concerning people's life, aerospace equipmen t, or nuclear control equi pment). also, when using this product for the equip- ment concerned with the control and safety of the transportation means, the traffic signal equip- ment, or various types of safety equipment, please do it after appl ying appropriate m easures to the product. 6.)despite our utmost efforts to im prove the quality and re liability of the product, faults will occur with a certain small probability, which is inevitable to a semi-c onductor product. therefore, you are encouraged to have suffic iently redundant or error preventive de sign applied to the use of the prod- uct so as not to have our product cause any social or public damage. 7.)please note that this product is not designed to be radiation-proof. 8.)customers are asked, if required, to judge by themselves if th is product falls under the category of strategic goods under the foreign exch ange and foreign trade control law. thine electronics, inc. e-mail: sales@thine.co.jp

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